Memory device for performing error correction code operation and redundancy repair operation
US9626244B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2014 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Mar 28, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.