Efficiency of cycle-reproducible debug processes in a multi-core environment
US9626265B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2015 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Jun 29, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.