Allocating lanes in a peripheral component interconnect express (‘PCIe’) bus
US9626319B2 · kind B2 · utility
2Cited by
20References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2013 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Dec 28, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Allocating lanes in a Peripheral Connect Interface Express (‘PCIe’) bus, including: determining, by a lane allocation module, performance capabilities of a device coupled to the PCIe bus; and allocating, by the lane allocation module, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.