SOI MOS device modeling method
US9626467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2012 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Sep 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a SOI MOS device modeling method. The SOI MOS device is one having a source-drain injection not reaching the bottom. The method comprises: a) establishing an overall model comprising a primary MOS device model simulating an SOI MOS device having the source-drain injection reaching the bottom, a source body PN junction bottom capacitance model simulating a source body PN junction bottom capacitance, and a drain body PN junction bottom capacitance model simulating a drain body PN junction bottom capacitance; and b) extracting parameters respectively for the primary MOS device model, the source body PN junction bottom capacitance model, and the drain body PN junction bottom capacitance model in the overall model. In the prior art, the source body junction bottom capacitance and the drain body junction bottom capacitance in the SOI MOS device having a source-drain injection not reaching the bottom affect the performances of the device. The modeling method of the present invention takes the effect into consideration, improves model precision, and can be effectively used for the simulation design of a device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.