Gate driving circuit
US9626895B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2015 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Aug 25, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A gate driving circuit is provided. The gate driving circuit includes a plurality of gate driving units sequentially coupled to each other. Each of the gate driving units includes a shift register and a de-multiplexer. The shift register receives a start pulse signal, and generates a first control signal and a second control signal according to the start pulse signal and a scan controlling signal, where when the shift register converts the first control signal into the second control signal, the shift register pulls down a voltage level of the first control signal according to the second control signal. The de-multiplexer receives a part of a plurality of clock signals for generating a plurality of gate signals sequentially according to the first control signal, where the clock signals are enabled sequentially, and enable periods of two sequential clock signals are partially overlapped with each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.