Systems, methods, and devices for parallel read and write operations
US9627016B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2015 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Dec 22, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.