6T static random access memory cell, array and memory thereof
US9627040B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2015 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Nov 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 6T static random access memory cell, array, and memory thereof are provided, in which the memory cell includes a first inverter, a second inverter, a first NMOS transistor, and a second NMOS transistor. A first high supply voltage and a low supply voltage are coupled to the first inverter. A second high supply voltage and the low supply voltage are coupled to the second inverter. The first NMOS transistor has a gate terminal coupled to a first word line. The first NMOS transistor has a source terminal coupled to the first node. The second NMOS transistor has a gate terminal coupled to a second word line, and the second NMOS transistor has a source terminal coupled to the second node. The first word line provides ON signals to turn on the first NMOS transistor, and the second high supply voltage provides a first boost voltage simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.