Structure and method for diminishing delamination of packaged semiconductor devices
US9627299B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 11, 2016 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Feb 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device (100) comprising a leadframe with a pad (101) and elongated leads (103) made of a base metal plated with a layer enabling metal-to-metal bonding; a semiconductor chip (110) attached to the pad, the chip having terminals. A metallic wire connection (130) from a terminal to a respective lead, the connection including a first ball bond by a first squashed ball (131) attached to the terminal, and a first stitch bond (132) attached to the lead. A second squashed ball (150) of the wire metal attached to the lead as a second ball bond adjacent to the first stitch bond (132). A package (170) of a polymeric compound encapsulating the chip, wire connection, second ball and at least a portion of the elongated lead, the compound adhering to the materials of the encapsulated entities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.