Patent · US Active

Wafer arrangement, a method for testing a wafer, and a method for processing a wafer

US9627341B2 · kind B2 · utility

0Cited by
2References
11Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 28, 2013
Grant dateApr 18, 2017
Priority date
Expiry dateOct 28, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/15788
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

According to various embodiments, a wafer arrangement may be provided, the wafer arrangement may include: a wafer including at least one electronic component having at least one electronic contact exposed on a surface of the wafer; an adhesive layer structure disposed over the surface of the wafer, the adhesive layer structure covering the at least one electronic contact; and a carrier adhered to the wafer via the adhesive layer structure, wherein the carrier may include a contact structure at a surface of the carrier aligned with the at least one electronic contact so that by pressing the wafer in direction of the carrier, the contact structure can be brought into electrical contact with the at least one electronic contact of the at least one electronic component.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.