Electronic circuits including a MOSFET and a dual-gate JFET
US9627374B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 2015 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Dec 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/87
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.