Three-dimensional transistor and methods of manufacturing thereof
US9627411B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 5, 2015 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Jun 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6218
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Three-dimensional (3D) transistors and methods of manufacturing thereof include a first semiconductor fin extending over a substrate. The first semiconductor fin has a vertical recess extending from a first sidewall of the first semiconductor fin toward a second sidewall of the first semiconductor fin opposite the first sidewall. A distance between two opposing sidewalls of the vertical recess decreases as the vertical recess extends toward the second sidewall of the first semiconductor fin. The device further includes a vertically recessed channel region between the second sidewall of the first semiconductor fin and a bottom of the vertical recess, source/drain (S/D) regions at opposite ends of the vertically recessed channel region, and a gate stack over the vertically recessed channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.