Analog to digital converters with oversampling
US9628106B1 · kind B1 · utility
1Cited by
3References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2016 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Jan 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/438
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.