Apparatus and method for length and rate variable LDPC encoder and decoder using shortening set allocator
US9628112B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 12, 2016 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | May 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6393
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for encoding data and for decoding data using LDPC (low density parity check) codes includes providing a mother LDPC matrix of a particular size. A data payload of a smaller size is encoded by shortening the mother matrix to a smaller daughter matrix corresponding in size to the data payload and using the smaller daughter matrix for the encoding. The portions of the mother matrix to be removed in the shortening are derived from a control signal. The encoded data is transmitted with the control signal so that the receiver can derive the portions of the mother matrix to be removed to obtain the daughter matrix. At the receiver, a mother matrix is shortened to a daughter matrix and is then used to decode the data. The data at the encoder may be further reduced by puncturing to remove selected information bits and selected parity bits. The decoder inserts the selected information bits and parity bits when decoding the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.