Mitigating a phase anomaly in an analogue-to-digital converter output signal
US9628123B2 · kind B2 · utility
1Cited by
2References
15Claims
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Key dates
| Filing date | Jan 28, 2016 |
| Grant date | Apr 18, 2017 |
| Priority date | — |
| Expiry date | Jan 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for mitigating a phase anomaly in an analogue-to-digital converter (ADC) output signal is disclosed. A plurality of codewords output by the ADC are received and information about an estimated level of interference between an output of the ADC and an input of the ADC due to the codeword is obtained for each codeword based on the logic values of bits in the codeword. In-phase (I) and quadrature (Q) corrections are obtained based on the information about the estimated level of interference, and applied to I and Q values obtained from the ADC output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.