Tracking deferred data packets in a debug trace architecture
US9632907B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2014 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Jun 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3636
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.