Two-tier distributed memory
US9632936B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2015 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Dec 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein are systems and methods to redirect data read requests from the first tier to the second tier of a two-tier distributed memory. The first tier includes memory modules with data sets. Data interfaces associated with the first tier memory modules, receive from a second tier including compute elements and associated cache memories, requests to fetch data from the first tier. If a data set has not recently been fetched by the second tier, then the data interface will send the data set from the first tier to the cache memory associated with the requesting compute element. If a data set has recently been fetched by the second tier, the data interface will redirect the requesting compute element to fetch the data set from the cache memory in which the data set is currently located.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.