Multi-source address translation service (ATS) with a single ATS resource
US9632948B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 23, 2014 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Jun 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/651
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an address translation system. The apparatus includes a memory management unit (MMU) that is operable to receive a translation request for an original address and translate the original address to a translated address as a second-level address translation service (ATS). The apparatus also includes an address translator having an associated cache to store the original address and the first translated address. The address translator is to translate memory addresses as a first-level address translation service (ATS). The address translator determines whether the transaction is to be processed using either the first-level ATS or the second-level ATS. The address translator translates a current memory address of the transaction to a current translated address using the first-level ATS or the second-level ATS based on the determination, The address translator also dispatches the transaction with the current translated address to a memory device where it may be further processed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.