Static timing analysis in circuit design
US9633148B2 · kind B2 · utility
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12References
16Claims
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Key dates
| Filing date | Sep 15, 2015 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Sep 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.