System and method for modeling through silicon via
US9633149B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2012 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Mar 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer implemented system comprises a processor programmed to analyze a circuit to determine a response of the circuit to an input radio frequency (RF) signal, for at least one of designing, manufacturing, and testing the circuit. An interposer model is tangibly embodied in a non-transitory machine readable storage medium to be accessed by the processor. The interposer model is processed by the computer to output data representing a response of a though substrate via (TSV) to the radio frequency (RF) signal. The interposer model comprises a plurality of TSV models. Each TSV model has a respective three-port network. One of the ports of each three-port network is a floating node. The floating nodes of each of the three-port networks are connected to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.