Circuit modification
US9633155B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2015 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Nov 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/68
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for modifying a circuit are described herein. In some examples, a method includes generating a set of testing data and detecting a predetermined modification to a translation path corresponding to a memory address mapping, the predetermined modification to change a physical memory address of the testing data associated with a virtual memory address to a second physical memory address of the testing data. The method can also include generating a test template comprising a first instruction to implement the predetermined modification and a second instruction comprising the second physical memory address in the translation path and transmitting the test template to the circuit for each of a plurality of software instruction threads. Furthermore, the method can include detecting a defect in the execution of the test template by the circuit and modifying the circuit to prevent the defect during execution of the test template.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.