Device having secure JTAG and debugging method for the same
US9633185B2 · kind B2 · utility
2Cited by
21References
21Claims
0Family size
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Key dates
| Filing date | Dec 1, 2014 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Dec 16, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of debugging a device which includes a plurality of processors is provided. The method includes verifying a request to initiate authentication that is provided to the device to a user; performing a challenge-response authentication operation between the user and the device in response to the request to initiate authentication being a request from a non-malicious user; activating or deactivating an access to a Joint Test Action Group (JTAG) port of each of the processors, based on access control information from the user; and permitting a debugging operation via an access that is activated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.