Semiconductor device including small pitch patterns
US9633851B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 1, 2016 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Mar 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate. The method also includes forming a plurality of discrete first sacrificial layers on the first region of the target material layer and a plurality of discrete second sacrificial layers on the second region of the target material layer, and forming first sidewall spacers on both sides of the discrete first sacrificial layers and the discrete second sacrificial layers. Further, the method includes removing the first sacrificial layers and the second sacrificial layers, and forming second sidewall spacers. Further, the method also includes forming discrete repeating patterns in the first region of the target material layer and a continuous pattern in the second region of the target material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.