Semiconductor package
US9633973B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2015 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Feb 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package is provided comprising a package substrate having an opening located in a central region thereof and a circuit pattern provided adjacent to the opening. A first semiconductor chip is located on the package substrate and includes first bonding pads. A pair of second semiconductor chips are spaced apart from each other across the opening and mounted between the package substrate and the first semiconductor chip. Each of the second semiconductor chips includes a second bonding pad. A connection element is further provided to electrically connect the second bonding pad to a corresponding one of the first bonding pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.