Systems and methods for inter-chip communication
US9633976B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2013 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Feb 21, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A quilt packaging system includes a first and second electronic device each comprising a plurality of edge surfaces at least a first edge surface of which comprises one or more interconnect modules disposed thereon. The first edge surface of the second electronic device is positioned contiguous to the first edge surface of the first electronic device, and at least one of the one or more interconnect nodules disposed on the first edge surface of the first electronic device is configured to be in physical contact with at least one of the one or more interconnect nodules disposed on the first edge surface of second electronic device so as to provide an electrical connection between the first and second electronic devices at the first edge surfaces of the first and second electronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.