Semiconductor devices having tapered active regions
US9634092B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2016 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Feb 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/258
Abstract
Provided is a finFET device. The finFET device may include an active region which protrudes vertically from a substrate, a channel region disposed on a center of the active region, a drain region disposed on one side surface of the channel region, and a source region disposed on the other side surface of the channel region, a gate insulating layer formed on two opposing side surfaces of the channel region and having a U-shaped cross-section, gate spacers formed on outer surfaces of the gate insulating layer, drain spacers formed on two opposing side surfaces of the drain region, and source spacers formed on two opposing side surfaces of the source region, and at least one of the two side surfaces of the drain region has a tapered part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.