Low temperature ohmic contacts for III-N power devices

US9634107B2 · kind B2 · utility

Assignee

• IMEC · BE

Inventors

• Brice De Jaeger · Leuven, BE
• Marleen Van Hove · Blanden, BE
• Stefaan Decoutere · Haasrode, BE
• Steve Stoffels · Haasrode, BE

Key dates

• Filing date: May 22, 2014
• Grant date: Apr 25, 2017
• Expiry date: May 22, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/256
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess.