Pipelining of clock guided logic using latches
US9634668B2 · kind B2 · utility
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7References
18Claims
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Key dates
| Filing date | Mar 17, 2014 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Mar 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/096
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This application discloses the technique to pipeline the Clock Guided Logic. Latch based storage elements are used in CGL based design such that when first stage CGL elements are in precharge phase the second stage CGL elements are in evaluate phase and vice-versa resulting into higher design throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.