Semiconductor device
US9634674B2 · kind B2 · utility
0Cited by
6References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 27, 2015 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Aug 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a PLL providing candidate clocks of different phases in response to a first clock received from a reader via an antenna, a phase difference detector detecting a phase difference between the first clock and a clock from the candidate clocks, a phase difference controller that selects another clock from the candidate clocks, and a driver that provides transmission data synchronously with the another clock to the reader.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.