Phase locked loop with jump-free holdover mode
US9634675B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2016 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Mar 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0991
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop with holdover mode has a loop filter for creating an offset frequency value for a controlled oscillator. The loop filter includes a register for storing the current offset frequency value the said controlled oscillator. A first multiplexer responsive to a holdover signal selects, depending on the quality of a reference signal, the output of the loop filter or a holdover queue to control the controlled oscillator. A second multiplexer responsive to the holdover signal selects for input to the register, depending on the quality of the reference signal, the sum of an output of the register and a value derived from the current phase difference between the output of the controlled oscillator and the reference signal or a current output value of the holdover queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.