Large-error detection and correction of digital sample sequence from analog-to-digital converter
US9634680B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2016 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Oct 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for detecting and correcting large errors during ADC operation. The system includes an ADC; an AAF at the input of the ADC, having bandwidth less than information bandwidth of the ADC; and a large-error detection and correction processing unit at the output of the ADC. The large-error detection and correction circuit includes an interpolation filter to determine values of predicted digital samples corresponding to actual digital samples in a sequence of digital samples from the ADC based on information from neighboring digital samples. A signal-delay circuit in parallel with the interpolation filter delays the actual digital samples by an amount of a lag from the interpolation filter. An adder determines differences between the predicted and actual digital samples, a matched filter detects a pattern of the differences, and a large-error detection processing unit determines whether a large error occurs based on the pattern of the differences.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.