Architectures and methods related to insertion loss reduction and improved isolation in switch designs
US9634718B2 · kind B2 · utility
1Cited by
3References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 11, 2015 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Jun 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2017/066
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Architectures and methods related to insertion loss reduction and improved isolation in switch designs. In some embodiments, a switching architecture can include a switch network having one or more switchable radio-frequency (RF) signal paths, where each path contributes to a parasitic effect associated with the switch network. The switching architecture can further include a parasitic compensation circuit coupled to a node of the switch network. The parasitic compensation circuit can be configured to compensate for the parasitic effect of the switch network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.