Powerline interference indication and mitigation for DSL transceivers
US9634780B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2014 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Apr 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2203/5408
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The present disclosure outlines mechanisms, systems, methods, techniques and algorithms that gateway devices and powerline communication (PLC) networks can follow to mitigate adverse effects from the aforementioned inter-network interference. Although the present disclosure provides implementation details for G.hn and VDSL2, the mechanisms, systems, methods, techniques and algorithms described herein are equally applicable to other similar technologies. Therefore, when referring to non-implementation specific systems, methods, techniques and algorithms the term PLC is used to refer to a powerline network and the term customer premises equipment (CPE) is used to refer to a home-gateway device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.