Parallel data switch
US9634862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2014 |
| Grant date | Apr 25, 2017 |
| Priority date | — |
| Expiry date | Mar 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/74
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet PKT to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD; (B) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA sends a subpacket of the packet PKT to the logic unit LD; or (C) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.