Method and apparatus for testing electrical connections on a printed circuit board
US9638742B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 13, 2009 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Mar 5, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49124
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test system and method for identifying open and shorted connections on a printed circuit board (PCB). An integrated circuit (IC) unit on the PCB is configured to generate a test signal on an output pin connected to a test pin on a second device, connector, or socket on the PCB. For a connection, the test signal is capacitively coupled to a detector plate proximal the second device. Based on the signal coupled to the detector, time domain analysis is performed on the coupled signal to determine if the test pin has a good connection to the PCB or if the pin is open or shorted. Analysis may include cross-correlating the coupled signal with a learned signal obtained from a known “good” PCB. The test pin may pass the test if the cross-correlation is within a specified threshold window. If the test fails, additional tests may be performed to troubleshoot the cause of the testing failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.