Array substrate, fault line repair method and display device
US9638973B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 18, 2016 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | May 18, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136272
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate, a fault line repair method thereof, and a display device are provided. The array substrate includes: a base substrate; a gate line and a signal line which are arranged on the base substrate, adjacent gate lines and adjacent signal lines crossing with each other to define a pixel region; and a pixel electrode located in the pixel region. The array substrate further includes a common electrode corresponding to the pixel electrode. The common electrode includes: a frame; a first strip-shaped connection part arranged in the frame and having both ends thereof connected with the frame; and a second strip-shaped connection part connected with the first strip-shaped connection part in a crossed manner and having both ends thereof disconnected from the frame. The signal line is parallel with the second strip-shaped connection part and located directly above or directly under the second strip-shaped connection part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.