Algorithm for vectorization and memory coalescing during compiling
US9639336B2 · kind B2 · utility
6Cited by
8References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2012 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Oct 25, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention sets forth a technique for reducing the number of assembly instructions included in a computer program. The technique involves receiving a directed acyclic graph (DAG) that includes a plurality of nodes, where each node includes an assembly instruction of the computer program, hierarchically parsing the plurality of nodes to identify at least two assembly instructions that are vectorizable and can be replaced by a single vectorized assembly instruction, and replacing the at least two assembly instructions with the single vectorized assembly instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.