Apparatus and method for heterogeneous processors mapping to virtual cores
US9639372B2 · kind B2 · utility
1Cited by
9References
22Claims
0Family size
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Key dates
| Filing date | Dec 28, 2012 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Nov 29, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.