Control mechanism for fine-tuned cache to backing-store synchronization
US9639466B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2012 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Apr 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0868
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention sets forth a technique for processing commands received by an intermediary cache from one or more clients. The technique involves receiving a first write command from an arbiter unit, where the first write command specifies a first memory address, determining that a first cache line related to a set of cache lines included in the intermediary cache is associated with the first memory address, causing data associated with the first write command to be written into the first cache line, and marking the first cache line as dirty. The technique further involves determining whether a total number of cache lines marked as dirty in the set of cache lines is less than, equal to, or greater than a first threshold value, and: not transmitting a dirty data notification to the frame buffer logic when the total number is less than the threshold value, or transmitting a dirty data notification to the frame buffer logic when the total number is equal to or greater than the first threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.