Write assist scheme for low power SRAM
US9640249B2 · kind B2 · utility
1Cited by
1References
19Claims
0Family size
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Key dates
| Filing date | May 20, 2014 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | May 20, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write-assist memory includes a memory supply voltage and a column of SRAM cells that is controlled by a pair of bit lines, during a write operation. Additionally, the write-assist memory includes a write-assist unit that is coupled to the memory supply voltage and the column of SRAM cells and has a separable conductive line located between the pair of bit lines that provides a collapsible SRAM supply voltage to the column of SRAM cells based on a capacitive coupling of a control signal in the pair of bit lines, during the write operation. A method of operating a write-assist memory is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.