Efficient compare operation
US9640250B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2016 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | May 16, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods relate to memory operations in a memory array. A compare operation is performed using a sense amplifier. True and complement versions of a search bit are compared with true and complement versions of a data bit stored in a data row of the memory array to generate true and complement sense amplifier inputs. The true and complement sense amplifier inputs are amplified in the sense amplifier to generate a single-ended match signal. The single-ended match signal can be aggregated with other single-ended match signals in the data row to determine whether there is a hit or miss for a compare operation on the entire data row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.