Method and circuit for programming non-volatile memory cells of a volatile/non-volatile memory array
US9640257B2 · kind B2 · utility
2Cited by
0References
15Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jan 7, 2015 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Jan 7, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/0081
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array including: a first volatile memory cell including first and second cross-coupled inverters between first and second storage nodes; a first non-volatile memory cell including at least one resistive element that can be programmed to take one of at least two resistive states; and a control circuit adapted to couple the first non-volatile memory cell to the first and second storage nodes in order to generate a current for programming the resistive state of the at least one resistive element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.