Semiconductor memory device
US9640265B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 9, 2016 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Sep 9, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, the semiconductor memory device includes a first memory cell and a word line. The first memory cell is capable of storing two or more bits of data. The word line is coupled with the first memory cell. a write operation repeat a program loop. The program loop includes a program operation and a verification operation. A program voltage is applied to the word line in the program operation. The write operation includes a first program loop and a second program loop subsequent to the first program loop. Program voltage is applied a first number of times in the first program loop. Program voltage is applied a second number of times in the second program loop. The second number of times is larger than the first number of times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.