Testability/manufacturing method to adjust output skew timing
US9640278B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 2015 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Dec 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an output driver circuit and a trimming circuit. The output driver circuit may be configured to (i) receive an input signal and a first control signal and (ii) generate an output signal. The output signal may be a delayed version of the input signal. A length of delay between the input signal and the output signal is determined in response to the first control signal. The trimming circuit may be configured to generate the first control signal in response to a second control signal. The trimming circuit is generally enabled to vary a value of the first control signal to minimize a phase difference between the output signal and an output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.