Apparatus and method for built-in test and repair of 3D-IC memory
US9640279B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2012 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Nov 7, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system-on-chip (SOC) (10) is interfaced with a memory (20) formed by a plurality of stacked memory integrated circuit dies (20a-20n). The SOC (10) includes a memory controller (100) that has a built-in self-test (BIST) system (1000) for performing the testing and repair of memory (20). BIST system (1000) includes a microcode processor (1130) that communicates externally to the SOC (10) through a Joint Test Action Group interface (120) and is coupled to a BIST state machine (1140) for executing a memory specific test sequence to detect faults in memory (20). The microcode processor (1130) further communicates with a repair state machine (1150) to execute memory specific repair procedures responsive to memory faults being detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.