Power semiconductor package having power semiconductor die in a support substrate with bar vias
US9640474B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2016 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Feb 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19042
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes an output inductor placed over a support substrate, a power semiconductor die having a bottom surface situated on the support substrate and a top surface having an active region, where the output inductor is coupled to the active region on the top surface of the support substrate, and where the support substrate includes a plurality of bar vias. The output inductor is a packaged component having at least two leads in electrical connection with the active region of the power semiconductor die. The support substrate further includes routing conductors in electrical connection with the active region of the power semiconductor die. The power semiconductor die includes a control transistor and a sync transistor connected in a half-bridge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.