Semiconductor package and method of fabricating the same
US9640513B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2015 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Apr 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first package having a first package substrate mounted with a lower semiconductor chip, and a second package having a second package substrate mounted with upper semiconductor chips. The second package substrate includes a chip region on which the upper semiconductor chips are mounted, and a connection region provided therearound. The chip region includes a first surface defining a first recess region and a second surface defining a first protruding portion. The upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.