Patent · US Active

Low-cost complementary BiCMOS integration scheme

US9640528B2 · kind B2 · utility

7Cited by
5References
18Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 17, 2015
Grant dateMay 2, 2017
Priority date
Expiry dateMar 17, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/60

Abstract

A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device is disclosed. The BiCMOS device includes a CMOS device in a CMOS region, a first CMOS well in the CMOS region, an NPN bipolar device in a bipolar region, a second CMOS well in the bipolar region, the second CMOS well being a collector sinker and being electrically connected to a sub-collector of the NPN bipolar device, where the first CMOS well in the CMOS region and the second CMOS well in the bipolar region form a p-n junction to provide electrical isolation between the CMOS device and the NPN bipolar device. The BiCMOS device further includes a PNP bipolar device having a sub-collector, the sub-collector of the PNP bipolar device being electrically connected to a third CMOS well.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.