Semiconductor device, layout design and method for manufacturing a semiconductor device
US9640605B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2015 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Apr 23, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first semiconductor structure having a first active region pattern density. The semiconductor device further includes a second semiconductor structure having a second active region pattern density, wherein the second semiconductor structure comprises a first resistive element. The semiconductor device further includes a third semiconductor structure having a third active region pattern density, wherein the third semiconductor structure includes a second resistive element. The second semiconductor structure is adjacent to the first semiconductor structure and adjacent to the third semiconductor structure. The first semiconductor structure, the second semiconductor structure and the third semiconductor structure do not overlap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.