Methods of fabricating semiconductor devices including hard mask patterning
US9640659B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2016 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Feb 23, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
Methods of fabricating semiconductor devices may include forming an isolation region that defines a plurality of fin active regions on a semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate, forming a first hard mask line that crosses first and second fin active regions and an edge bard mask line that crosses an edge fin active region, and forming a gate cut mask having a plurality of gate cut openings. The plurality of gate cut openings may include first and second gate cut openings that have a first width and are adjacent to the first and second fin active regions, respectively, and an edge gate cut opening that is adjacent to the edge fin active region and has a second width that is greater than the first width but smaller than twice a size of the first width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.