Applying force voltage to switching node of disabled buck converter power stage
US9641077B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2015 |
| Grant date | May 2, 2017 |
| Priority date | — |
| Expiry date | Mar 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/40
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Reliability of a buck power stage may be enhanced by extending the maximum input voltage able to be withstood in the disabled (non-switching) state. During device qualification/testing, a power management unit (PMU) in the disabled state may have its input node subjected to greater than a maximum input voltage permitted for reliability (Vmax). Under such conditions, a force voltage (Vforce) may be selectively applied to the PMU switching node in the disabled state. For a given input voltage (VIN), this reduces voltage across the non-switching transistors of the power stage (and hence the resulting stress) to below Vmax. In certain embodiments, the Vforce applied to the switching node is of a fixed magnitude. In other embodiments, the Vforce applied to the switching node is of a magnitude varying with input voltage. Embodiments may be particularly suited to implement power management for a System-On-Chip (SoC).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.